The performance of many integrated circuits (ICs) can be improved by using on-chip, self-calibration techniques. On-chip, self-calibration techniques are desirable because they typically do not consume expensive production time and can track physical changes in a system due to aging, temperature changes and the like. Moreover, self-calibration techniques can perform accurate calibration on-line in normal operating environments.
Applying on-chip, self-calibration techniques to ICs used in high-speed data communication applications is especially desirable due to the many sources of non-linearity and errors (e.g., offset, device mismatch, common-mode sensitivity, pre-amp gain compression, etc.). A typical high-speed data link receiver can include many receiver samplers for sampling data values (for example, in quadrature) and edges, and for adjusting equalization (i.e., adaptation) and testing data eye size. Each receiver sampler can include one or more digital-to-analog converters (DACs) for adjusting sampling threshold voltage levels and providing other functionality (e.g., adaptation and performance monitoring). Each of these DACs can be a source of errors, which, if uncompensated, could result in a degradation of the overall system performance. Performance degradations can include, without limitation, loss of voltage margins due to imperfect offset cancellations or threshold voltage settings and instability of adaptation algorithms, which, in part, rely on the overall system being linear (i.e., having a linear transfer function).